1. Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device, and particularly to a reduction in a field and in a gate capacitance of a gate insulating film in a JFET region of a MOSFET.
2. Description of the Background Art
According to Japanese Patent No. 4049095 disclosing a semiconductor device, a groove (protrusion) is formed on a surface of a drift region, and a p-well region is formed in a bottom portion of the groove. A gate insulating film is thicker at a side surface of the groove than at other portions.
In such a configuration, the gate insulating film in a JFET region is arranged on an upper side of the protrusion of the groove, to thereby suppress an electric field that is applied to the gate insulating film in the JFET region when a high voltage is applied to the drain side while a MOSFET is OFF.
According to Japanese Patent Application Laid-Open No. 2009-32919, in a planar MOSFET, a gate insulating film (oxide film) is thicker in a JFET region than in the other region so that an electric field applied to a JFET oxide film is suppressed.
The semiconductor devices disclosed in Japanese Patent No. 4049095 and Japanese Patent Application Laid-Open No. 2009-32919 involve a problem that the intensity of the electric field applied to the gate insulating film in the JFET region is not yet sufficiently suppressed, and also a problem that the gate capacitance increases to make a high-speed operation difficult.